1. Field of the Invention
The present invention relates to a semiconductor memory device for storing data of plural bits in a single memory cell constituted by a single transistor.
2. Description of the Related Art
In a conventional read-only memory (ROM), one memory cell is constituted by one transistors. There are two methods of storing data in each memory cell. In a first method, data is stored in the memory cell by selecting either a high-level or low-level threshold voltage (Vth) of the transistor as the memory cell. In a second method, whether data is stored in the memory cell is determined by whether the drain of the transistor as the memory cell is connected to a column line or not.
When data is stored by the first method, the data can be read by applying a predetermined potential to a row line connected to the gate of the associated memory cell transistor. In this case, the transistor with the high-level threshold voltage is turned off and the transistor with the low-level threshold voltage is turned on. Thus, data "1" or data "0" is read from the memory cell. When data is stored by the second method, the data can be similarly read by applying a predetermined potential to the row line.
When a predetermined potential is applied to the row line, the transistor is-rendered conductive. If the. drain of the transistor is connected to the column line, the column line is discharged through this memory cell transistor If the drain is not connected to the column line, the column line is not discharged even if the memory cell transistor is rendered conductive. Thus, the column line has two potential levels, i.e. a discharged level and a charged level, depending on whether the drain of the memory cell transistor is connected to the column line. Thereby, data "1" or data "0" is read out.
In either method, however, data of only one bit can be stored in one memory cell. Thus, in the prior art, in order to increase the memory capacity, the chip size increases inevitably.
In order to reduce the chip size, a memory cell in which data of two bits is stored has been proposed. FIG. 27 shows an example of this type of conventional semiconductor memory device. The data of two bits is stored in a single memory cell.
In FIG. 27, reference numeral 1 denotes a column decoder for decoding column address signals a.sub.0, /a.sub.0, a.sub.1, /a.sub.1, . . . ; numeral 2 denotes insulated gate type field effect transistors (hereinafter referred to as "MOS transistors") for column selection, which are controlled by decode outputs from the column decoder 1; numeral 3 denotes column lines; numeral 4 denotes a row decoder for decoding row address signals A.sub.1, /A.sub.1, A.sub.2, /A.sub.2, . . . , excluding lowest-bit signals A.sub.0 and /A.sub.0 ; numeral 5 denotes row lines; numeral 6 denotes MOS transistors constituting memory cells driven selectively by the row lines 5; numeral 7 denotes a load MOS transistor for charging the column lines 3; and symbol P denotes a common node of the MOS transistors 2. The MOS transistors 2 and 6 are N-channel enhancement type transistors, and the transistor 7 is an N-channel depletion type or a P-channel enhancement type transistor.
As is shown in FIG. 28, for example, the threshold voltage Vth of each memory cell transistor 6 is preset at one of four threshold voltages Vth1 to Vth4 (Vth4&lt;Vth3&lt;Vth2&lt;Vth1) in accordance with data units D0 and D1 of two bits to be stored.
FIG. 29 shows the structure of a circuit for outputting data stored in each memory cell by detecting the potential of each column line 3. In FIG. 29, a terminal 11 is connected to the common node P of the column selection transistors 2.
A potential generating circuit 12 comprises an enhancement type MOS transistor 15, an enhancement type MOS transistor 16 and a depletion type MOS transistor 17. The threshold voltage of the transistor 15 is set at one of the aforementioned four thresholds, i.e. Vth4. A power supply voltage VC is constantly applied to the gate of the transistor 15 and the transistor 15 is equivalent to the selected memory cell transistor 6 having the threshold voltage Vth4. The enhancement type MOS transistor 16 has the same dimensions as the column selection MOS transistor 2, and the transistor 16 is normally set in the on-state with voltage VC applied to the gate thereof. The depletion type MOS transistor 17 has the same dimensions as the load MOS transistor 7. The potential generating circuit 12 generates a potential V.sub.1 equal to the potential of the node P at the time the column line 3 has been discharged through the memory cell transistor 6 having the threshold voltage Vth4.
Like the potential generating circuit 12, potential generating circuits 13 and 14 generate potentials V.sub.2 and V.sub.3, respectively. The potentials V.sub.2 and V.sub.3 are equal to the potential of the column line 3 at the time the column line 3 has been discharged through the memory cell transistor 6 having the threshold voltage Vth3 and Vth2, respectively. In the potential generating circuit 13, the MOS transistor 15 is replaced with an enhancement type MOS transistor 18 set at the threshold voltage Vth3. In the potential generating circuit 14, an enhancement type MOS transistor 19 set at the threshold voltage Vth2 is substituted. The generated voltages V.sub.1 to V.sub.3 have the relationship, V.sub.1 &lt;V.sub.2 &lt;V.sub.3.
Each of the voltage comparing circuits 20, 21 and 22 comprises two enhancement type MOS transistors 23 and 24 and depletion type MOS transistors 25 and 26. The voltage comparing circuit 20 compares potential Vp at the node P applied to the terminal 11 with the output potential V.sub.1 of the potential generating circuit 12. When the potential Vp is equal to or lower than V.sub.1, the potential comparing circuit 20 outputs a "1"-level signal a, and when the potential Vp is higher than V.sub.1, it outputs a "0"-level signal a. The voltage comparing circuit 21 compares the potential Vp at node P with the output potential V.sub.2 of the potential generating circuit 13. When the potential Vp is equal to or lower than V.sub.2, the potential comparing circuit 21 outputs a "1"-level signal b, and when the potential Vp is higher than V.sub.2, it outputs a "0"-level signal b. The voltage comparing circuit 22 compares the potential Vp at node P with the output potential V.sub.3 of the potential generating circuit 14. When the potential Vp is equal to or lower than V.sub.3, the potential comparing circuit 22 outputs a "1"-level signal c, and when the potential Vp is higher than V.sub.3, it outputs a "0"-level signal c.
Reference numerals 27, 28 and 29 denote NOR logic circuits, and numeral 30 denotes an inverter circuit 30. The output signal c of the voltage comparing circuit 22 and the lowest-bit row address signal A.sub.0 are supplied to the NOR logic circuit 27. The output signal b of the voltage comparing circuit 21 is supplied to the NOR logic circuit 28 via the inverter circuit 30, and the row address signal /A.sub.0 is also supplied to the NOR logic circuit 28. Output signals from the NOR logic circuits 27 and 28 as well as the output signal a of the voltage comparing circuit 20 are supplied to the NOR logic circuit 29.
An output buffer circuit (BC) 31 detects the output signal from the NOR logic circuit 29 and outputs "1"-level data or "0"-level data A chip selection signal CS controls output of data from the output buffer circuit 31.
All the transistors are N-channel transistors, like those shown in FIG. 27.
The operation of the circuit with the above structure will now be described. When row address signals are input to the row decoder 4, the row decoder 4 selects one of the row lines 5 and sets it at "1" level. When column address signals are input to the column decoder 1, the column decoder 1 selects and activates one of the column selection transistors 2 The memory cell transistor 6 located at the intersection of the selected column line 3 and row line 5 is driven, and this column line 3 is charged or discharged through the memory cell transistor 6. If the threshold voltage of the transistor 6 is Vth4, the potential of the column line 3 is V.sub.1 at the time the column line 3 has been discharged. The potential V.sub.1 of the column line 3 is compared with voltages V.sub.1, V.sub.2 and V.sub.3 in the voltage comparing circuits 20, 21 and 22. As a result, all signals a, b and c are set at "1" level. At this time, since the "1" level signal a is input to the NOR logic circuit 29, the output of the NOR logic circuit 29 is "0" level, irrespective of the output signals of the NOR logic circuits 27 and 28. If the output buffer circuit 31 is activated by the chip selection signal CS, the "0" level signal is output as data stored in the selected memory cell transistor 6 from the output buffer circuit 31. In other words, whether the address signal A.sub.0 is at "0" level or "1" level, the output signal of the NOR logic circuit 29 is at "0" level and a "0" level signal is output from the output buffer circuit 31.
Thus, data D0 and D1 (D0=D1="0") of two bits, as shown in FIG. 28, are output from one memory cell.
If the threshold voltage of the memory cell transistor 6 located at the intersection of the selected column line 3 and row line 5 is vth3, the potential of the column line 3 is V.sub.2 at the time the column line 3 has been discharged by the memory cell transistor 6. In this case, only the output signal a of the voltage comparing circuit 20 is at "0" level, and the output signals b and c of the other two voltage comparing circuits 21 and 22 are at "1" level. If the row address signal A.sub.0 ="1" and the row address signal /A.sub.0 ="0", the output signal of the NOR logic circuit 28 is "1" level since the output signal of the inverter circuit 30 is "0" level. The output signal of the NOR logic circuit 29 is "0" level. Accordingly, the "0" level signal is output from the output buffer circuit 31.
On the other hand, if the row address signal A.sub.0 ="0" and the row address signal /A.sub.0 ="1", the output signals of both NOR logic circuits 27 and 28 are "0" level. Since the signal a is also "0" level, the output signal of the NOR logic circuit 29 is "1" level. Accordingly, the "1" level signal is output from the output buffer circuit 31.
In this case, data D0 and D1 (D0="0", D1="1") of two bits, as shown in FIG. 28, are output from one memory cell in accordance with the "1" level and "0" level of the address signal A.sub.0.
If the threshold voltage of the memory cell transistor is Vth2 or Vth1, the potentials of the column line 3 are V.sub.3 and V.sub.4, respectively, at the time the charge or discharge of the column line 3 has been completed. When the potential of the column line reaches V.sub.3, the output signals a and b of both voltage comparing circuits 20 and 21 are "0" level and the output signal c of the voltage comparing circuit 22 is "1" level. In this case, the output signal of the NOR logic circuit 29 is "1" level, whether the row address signal A.sub.0 ="1" and the row address signal /A.sub.0 ="0", or the row address signal A.sub.0 ="0" and the row address signal /A.sub.0 ="1", because all input signals of this NOR logic circuit 29 are "0" level. Thus, data D0 and D1 (D0=D1="1") of two bits, as shown in FIG. 28, are output from one memory cell.
On the other hand, when the potential of column line 3 reaches V.sub.4, data D0 and D1 (D0="1", D1="0") of two bits, as shown in FIG. 28, are output from one memory cell. Specifically, when all the signals a, b and c are "0" level and when the address signal A.sub.0 ="1" and the address signal /A.sub.0 ="0", the output of the NOR logic circuit 27 is "0" level and the output of the inverter circuit 30 is "1" level. Accordingly, the output of the NOR logic circuit 28 is "0" level. Thus, all input signals to the NOR logic circuit 29 are "0" level, and the output of the NOR logic circuit 29 is "1" level.
Furthermore, if the address signal A.sub.0 ="0" and the address signal /A.sub.0 ="1", all inputs to the NOR logic circuit 27 are "0" level. Thus, the output of the NOR logic circuit 27 is "1" level. Since one of the inputs to the NOR logic circuit 29 is "1" level, the output from the NOR logic circuit 29 is "0" level. Accordingly, when the address signal A.sub.0 ="1", the "1" level signal is output as the stored data of the selected memory cell from the output buffer circuit 31. When the address signal A.sub.0 ="0", the "0" level signal is output as the data from the output buffer circuit 31. In other words, if the column line potential is V.sub.4, data D0 and D1 (D0="1", D1="0") of two bits, as shown in FIG. 28, are output from one memory cell.
With the above circuit, two-bit data of two addresses is stored in one memory cell. Thus, double data can be stored in the memory cell without increasing the chip size. In other words, the chip size can be remarkably reduced, with the same memory capacity as in the prior art.
In the above circuit, the potential of the column line 3 at the time of completion of charge or discharge is determined by presetting the threshold voltage of the memory cell transistor 6 at one of four threshold voltages. The potential of the column line 3 at the time of completion of charge or discharge can be determined by providing four kinds of channel widths W1, W2, W3, W4 of the transistors 6, as shown in FIG. 30, or by providing four kinds of channel lengths L1, L2, L3, L4, as shown in FIG. 31, instead of the four kinds of threshold voltages Vth1, Vth2, Vth3 and Vth4. When the potentials of the column lines 3 are determined by the channel widths of the transistors 6, if the channel widths have the relationship of W4&lt;W3&lt;W2&lt;W1, the potentials of the column lines 3 at the time of completion of charge or discharge, i.e. the potentials Vp at the node P, have the relationship of Vp1&lt;Vp2&lt;Vp3&lt;Vp4. The potentials Vp1 to Vp4 are equal to the potentials of the column lines charged or discharged by the transistors of channel widths W1 to W4, respectively. When the potentials of the column lines 3 are determined by the channel lengths of the transistors 6, if the channel lengths have the relationship of L1&lt;L2&lt;L3&lt;L4, the potentials Vp at the time of completion of charge or discharge have the relationship of Vp1&lt;Vp2&lt;Vp3&lt;Vp4. The potentials Vp1 to Vp4 are equal to the potentials of the column lines charged or discharged by the transistors of channel lengths L1 to L4, respectively. When the potentials of the column lines 3 are to be set by the channel widths or channel lengths of the transistors 6, the channel widths of the transistors 15, 18 and 19 of the potential generating circuits 12, 13 and 14 need to be set at W1, W2 and W3, respectively, or the channel lengths thereof need to be set at L1, L2 and L3, respectively. In each case, the memory size can be reduced, compared to the prior art. In the case of setting the potentials of the column lines 3 at the time of completion of charge or discharge at four levels by the threshold voltages of the transistors 6, the memory cell size can be reduced to a minimum. On the other hand, at least three manufacturing steps need to be additionally provided, as compared to the prior art, at the time of setting four threshold voltages, i.e. at the time of writing data. However, if the data of the memory cell is determined by providing four channel widths or four channel lengths of the transistors 6, the increase in number of manufacturing steps can be prevented.
In the case of storing data by varying the channel width of the transistor, the number of manufacturing steps does not increase. However, since the step of setting the channel width is performed at the early stage of manufacture, a long period of time of manufacture is required from the reception of a client's order to the delivery of a finished product. In the case of varying the channel length, data is stored at the time of forming gate electrodes. Thus, the time of manufacture is less than in the case of varying the is channel width, but is greater than in the case of storing data by varying the threshold voltage.
Specifically, in the case of storing data by varying the threshold voltage, impurities for determining the threshold voltage of the memory cell are introduced by ion implantation in the channel region through the gate electrode after the gate electrode of the memory cell is formed. Accordingly, the time of manufacture is made less than in the case of varying the channel width or channel length. However, since data is stored by varying the threshold voltage, a plurality of masks need to be used. In addition, ion implantation with different dosages must be performed with different masks according to data to be stored, and thus the number of manufacturing steps increases.